1. Field of the Invention
The invention relates to a process of forming shallow trench isolation. More particularly, the present invention relates to a manufacturing method of forming shallow trench isolation with chamfered corners.
2. Description of the Related Art
Recently, as the manufacturing techniques of semiconductor integrated circuits develop, the number of devices in a chip has increased. The size of the device also decreases as the degree of integration increases. The line width used in manufacturing, lines has decreased from sub-micron to quarter-micron, or even smaller. Regardless of the reduction of the size of the device, adequate insulation or isolation must be provided among individual devices in the chip so that good element characteristics can be achieved. This technique is called device isolation technology. The main object is to form an isolation region, reducing the size of the isolation as much as possible while assuring good isolation effect to allow larger chip space for more devices.
Among different device isolation techniques, LOCOS and shallow trench isolation region manufacturing methods are the two most used methods. In particular, as the latter has a small isolation region and can keep the substrate level after the process is finished, it is the semiconductor manufacturing method obtaining the most attention.
The conventional manufacturing method for a shallow trench isolation region comprises forming a dielectric layer to fill a trench on a substrate by chemical vapor deposition (CVD), and etching back the dielectric layer on the substrate to remove the redundant dielectric layer. However, as the density of the semiconductor integrated circuits increases and the size of the elements decreases, the above mentioned deposition experiences problems in step coverage and cannot completely fill the trench. This influences the isolation effect among elements.
As a result of filling the entire trench which has a high aspect ratio, recently, high-density plasma chemical vapor deposition (HDPCVD) is used to form a dielectric layer on the substrate instead of CVD. In HDPCVD, the dielectric layer is deposited using O2 and SiH4 gases.
FIGS. 1A-1C show a conventional fabrication process of a shallow trench isolation. In FIG. 1A, a pad oxide layer 12 is deposited on a substrate 10 such as Si substrate, wherein the thickness of the pad oxide layer 12 is about 50-200 Å. The pad oxide layer 12 is formed using thermal oxidation or CVD. Thereafter, a silicon nitride layer 14 is deposited on the pad oxide layer 12 using CVD, and the thickness of the silicon oxide layer 14 is 500-2000 Å. A mask layer thereby consists of the pad oxide layer 12 and the silicon nitride layer 14. Next, a patterned photoresist layer 13 is defined on the silicon nitride layer 14 and the pad oxide layer 12 using photolithography and etching techniques to expose a portion of the substrate 10 where the shallow trench isolation is formed.
Next. In FIG. 1B, the exposed portion of the substrate 10 is etched using the silicon nitride layer 14 and the pad oxide layer 12 as a mask to form a trench 15, and the depth of the trench 15 is about 3500-5000 Å. Then, a thin liner layer 16 is formed on the sidewall of the trench 15 using thermal oxidation process, and the thickness of the liner layer 16D is 180 Å.
As shown in FIG. 1C, in HDPCVD, a dielectric layer 18 is deposited and fills the trench 15, wherein O2 and SiH4 are reactants.
As shown in FIG. 2, due to the opening of the trench narrowing and/or the aspect ratio of the trench increasing, for example the opening width may be less than 0.11 μm and/or the aspect ratio larger than 4, the dielectric layer 18 deposited on the silicon nitride layer 14 may cover the opening of the trench 15 in the HDPCVD process, such that the dielectric layer 18 cannot fill the trench 15 completely and a void 20 is formed in the trench, resulting in poor insulation quality of the shallow trench isolation region.
Because the properties of the dielectric layer 18 are similar to those of the pad oxide layer 12, when etchant is used to dip pad oxide layer 12, the shallow trench isolation region 28 is inevitably etched so that the corner 22 of the trench 15 is exposed and an indentation 30 is formed adjacent to the corner 22 of the trench 15.
Thus, when the gate oxide layer and gate conductive layer are formed later, the conductive layer deposited in the indentation 30 is not easily removed and a short circuit between the adjacent transistors easily occurs. In addition, since the gate oxide layer at the corner 22 of the the trench 15 is thinner than other places, a parasitic transistor is formed. When current goes through this parasitic transistor, as the curvature radius of the corner 22 of the trench 15 is small, the electric fields concentrate and the Fowler-Nordheim current increases, hence the insulating property of the gate oxide layer of the corner 22 degrades, resulting in abnormal element characteristics. For example, there may be a kink effect in I-V curvature of Id and Vg, which generates a double hump.